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Physical Coding Sublayer
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Physical Coding Sublayer : ウィキペディア英語版
Physical Coding Sublayer
The Physical Coding Sublayer (PCS) is a networking protocol sublayer in the Fast Ethernet, gigabit Ethernet, and 10 Gigabit Ethernet standards. It resides at the top of the physical layer (PHY), and provides an interface between the Physical Medium Attachment (PMA) sublayer and the Media Independent Interface (MII). It is responsible for data encoding/decoding, scrambling/descrambling, alignment marker insertion/removal, block and symbol redistribution, and lane block synchronization and deskew.
== Description ==
The Ethernet PCS sublayer is at the top of the Ethernet physical layer (PHY). The hierarchy is as follows:
* Data Link Layer (Layer 2)
*
* LLC (Logical Link Control Sublayer)
*
* MAC (Media Access Control Sublayer)
*
*
* RS (Reconciliation Sublayer) - This sublayer processes PHY Local/Remote Fault messages and handles DDR conversion
* PHY Layer (Layer 1)
*
* PCS (Physical Coding Sublayer) - This sublayer determines when a functional link has been established, provides rate difference compensation, and performs coding such as 64b/66b encoding and x^+x^+1 scrambling/descrambling
*
* PMA (Physical Medium Attachment Sublayer) - This sublayer performs PMA framing, octet synchronization/detection, and x^7+x^6+1 scrambling/descrambling
*
* PMD (Physical Medium Dependent Sublayer) - This sublayer consists of a transceiver for the physical medium

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